The present invention relates generally to a semiconductor device, and more particularly to an on die termination device that controls a terminal resistance value in accordance with a test signal.
A semiconductor device, such as a memory device, transmits/receives data to/from external systems. If an impedance of the semiconductor device is different from an impedance of the bus line, which is connected with the external system to transmit the data, the data could possibly be reflected.
Therefore, the semiconductor device includes an on die termination (hereinafter, ODT) device that matches the impedance of the systems interfaced with one another. The ODT prevents the transmittance signal from being reflected allowing the semiconductor device to support high-speed operations.
FIG. 1 is a drawing showing a general ODT device equipped in a Double Data Rate (DDR2) Dynamic Random Access Memory (DRAM). The ODT device of FIG. 1 includes an ODT control unit 1 and an ODT resistor unit 2.
The ODT control unit 1 receives an ODT enable signal EN having a value corresponding to the set state of an extended mode register set (EMRS; not shown), and the ODT control unit generates and outputs a pullup driving signal PU and a pulldown driving signal PD according to the ODT enable signal EN.
The ODT resistor unit 2 includes a pullup resistor unit 2a and a pulldown resistor 2b connected in series between terminals to which a power supply voltage VDDQ and a ground voltage VSS are applied. An output node ND1 is generated between the pullup resistor unit 2a and the pulldown resistor unit 2b. 
The pullup resistor unit 2a includes a PMOS transistor P1 and a resistor R1 that are connected in series. The pulldown resistor unit 2b includes a NMOS transistor N1 and a resistor R2 that are connected in series.
The PMOS transistor P1 is driven by the pullup driving signal PU, and the NMOS transistor N1 is driven by the pulldown driving signal PD. If the PMOS transistor P1 and the NMOS transistor N1 are driven, the power supply voltage VDDQ is applied to the resistor R1 and the ground voltage VSS is applied to the resistor R2. Subsequently, the voltage controlled by the resistors R1, R2 is applied to the output node ND1, and the voltage applied to the voltage node ND1 is outputted as an output signal DQ.
It is preferable that the level of the output signal DQ be set to VDDQ/2. As such, the resistance values of the resistors R1, R2 are designed in consideration of the level of the output signal DQ. However, the actual resistance values of the resistors R1, R2 may differ from the designed value due to various factors, such as a change in production process, a change in power supply voltage, or a temperature change.
In addition, when analyzing the ODT resistance, it is necessary to control the resistance values of the pullup resistor unit 2a and the pulldown resistor unit 2b. However, if the pullup resistor unit 2a and the pulldown resistor unit 2b are designed as shown in FIG. 1, it is difficult to control the resistance values of the pullup resistor unit 2a and the pulldown resistor unit 2b. Therefore, it is difficult to efficiently analyze the ODT resistance.
After the semiconductor chip is produced, a partial portion of the metal layer having the resistor R1, R2 must be corrected by performing a focused ion beam (hereinafter, FIB) process. However, in this case, the contact resistance of a contact formed in the top portion of the metal layer can change the resistance values of the resistors R1, R2. As such, a problem exists in a typical ODT device, in that it is difficult to change the resistance value of the resistor R1, R2 while analyzing the ODT resistance.